RESEARCH PAPERS: Natural and Mixed Convection

Liquid Immersion Cooling of a Substrate-Mounted Protrusion in a Three-Dimensional Enclosure: The Effects of Geometry and Boundary Conditions

[+] Author and Article Information
D. E. Wroblewski

Department of Aerospace and Mechanical Engineering, Boston University, Boston, MA 02215

Y. Joshi

Department of Mechanical Engineering and CALCE Electronics Packaging Center, University of Maryland, College Park, MD 20742

J. Heat Transfer 116(1), 112-119 (Feb 01, 1994) (8 pages) doi:10.1115/1.2910844 History: Received October 01, 1992; Revised June 01, 1993; Online May 23, 2008


A three-dimensional computational study of steady natural convection cooling of a substrate-mounted protrusion (chip) in a rectangular enclosure filled with dielectric liquid is described. Energy is generated in the chip at a uniform rate Q . Conduction within the chip and substrate are accounted for in the model, as is the coupled natural convection in the surrounding liquid. The nondimensional governing equations with the appropriate boundary conditions have been solved in the primitive variable form for Ra = 108 using a fully implicit finite volume formulation. Baseline computations have been performed for a cubical enclosure with a centrally placed silicon chip on a vertical alumina substrate, which forms one enclosure wall. The cooling liquid was Fluorinert FC 75 resulting in Pr = 25. The effects of conductive spreading along the substrate were found to be quite pronounced due to the low thermal conductivity of the liquid. Effects of chip and enclosure sizes on the maximum chip temperatures displayed a strong dependence on the substrate to fluid thermal conductivity ratio, RS . Conditions for the validity of two-dimensional approximations were investigated for large and small RS . Two other thermal boundary conditions on the enclosure walls were also considered, with the smallest chip temperatures found for the top and one vertical sidewall cooled condition. For the baseline boundary conditions a numerical correlation for the maximum chip temperature was obtained.

Copyright © 1994 by The American Society of Mechanical Engineers
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