RESEARCH PAPERS: Micro/Nanoscale Heat Transfer

Thermal Conductivity Measurements of Ultra-Thin Single Crystal Silicon Layers

[+] Author and Article Information
Wenjun Liu, Mehdi Asheghi

Mechanical Engineering Department, Carnegie Mellon University, Pittsburgh, PA 15213

J. Heat Transfer 128(1), 75-83 (Jun 24, 2005) (9 pages) doi:10.1115/1.2130403 History: Received March 06, 2004; Revised June 24, 2005

Self-heating in deep submicron transistors (e.g., silicon-on-insulator and strained-Si) and thermal engineering of many nanoscale devices such as nanocalorimeters and high-density thermomechanical data storage are strongly influenced by thermal conduction in ultra-thin silicon layers. The lateral thermal conductivity of single-crystal silicon layers of thicknesses 20 and 100nm at temperatures between 30 and 450K are measured using joule heating and electrical-resistance thermometry in suspended microfabricated structures. In general, a large reduction in thermal conductivity resulting from phonon-boundary scattering is observed. Thermal conductivity of the 20nm thick silicon layer at room temperature is nearly 22Wm1K1, compared to the bulk value, 148Wm1K1. The predictions of the classical thermal conductivity theory that accounts for the reduced phonon mean free paths based on a solution of the Boltzmann transport equation along a layer agrees well with the experimental results.

Copyright © 2006 by American Society of Mechanical Engineers
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Figure 1

(a) The optical microscope image of the suspended structure. Cross sections of (b) the metal/silicon and (c) the metal (aluminum or CoFe) suspended structures, which are used to obtain the thermal conductivity data for silicon layer.

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Figure 2

Fabrication process of 100nm silicon film

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Figure 3

Fabrication process of 20nm silicon film

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Figure 4

Temperature dependent thermal conductivity data of the 100nm thick aluminum and 75nm CoFe layers as a function of temperature, which are subsequently used to obtain the thermal conductivity data for 100nm and 20nm thick silicon layers, respectively. The uncertainties in the data are less than 5%, which is on the order of size of the “symbols.” As a result, the uncertainty bars are not shown in this plot.

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Figure 5

Curve fits for thermal conductance along the length of the CoFe and CoFe+silicon suspended structures using Eqs. 5,7 to the electrical resistivity data at room temperature. The fitted thermal conductivity data for CoFe layer is subsequently used to extract the thermal conductivity of the 20nm thick silicon layer. The uncertainties in the measured electrical resistivity data are less than 2%, which is on the order of size of “symbols.” The gray shaded areas show the ±5% and ±7% variations in thermal conductance of the CoFe and CoFe+silicon structures based on the predictions of the Eqs. 5,7.

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Figure 6

The temperature dependent thermal conductivity data for the silicon layers of 20 and 100nm thickness. The estimated uncertainties for 20nm thick silicon layer are on the order of 12%, 8% at 30K and 300K. For 100nm silicon layer, the estimated uncertainties are on the order of 9% and 15% at 100K and 300K, respectively.

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Figure 7

Thermal conductivity of silicon layer and wires, at room temperature, as a function of thickness. Predictions based on Boltzmann transport equation (BTE) agree reasonably well with the experimental data (8,10) for thin silicon film. For nanowires, the predications are different from the reported data (18) for D=22nm by nearly 30%.

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Figure 8

Lateral thermal conductivity data and predictions for thin silicon layers at high temperatures. The estimated uncertainties for 20nm thick silicon layer are on the order of 8%, 6% at 300K and 400K. For 100nm silicon layer, the estimated uncertainties are in the order of 15% and 22% at 300K and 450K, respectively

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Figure 9

The uncertainty related to 5% variation of the metal film thickness (dm=75nm) results in nearly ±10% uncertainty in the measurement of the thermal conductivity of 20nm thick silicon layer at room temperature. For thermal conductivity measurements of 10nm and 5nm thick silicon layers with uncertainty on the order of ∼±15%, metal layer thickness should be reduced to 50nm and 20nm, respectively.



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