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Research Papers: Electronic Cooling

# 3D Integrated Water Cooling of a Composite Multilayer Stack of Chips

[+] Author and Article Information
Fabio Alfieri, Manish K. Tiwari, Igor Zinovik

Department of Mechanical and Process Engineering, Laboratory of Thermodynamics in Emerging Technologies, ETH Zurich, 8092 Zurich, Switzerland

Dimos Poulikakos

Department of Mechanical and Process Engineering, Laboratory of Thermodynamics in Emerging Technologies, ETH Zurich, 8092 Zurich, Switzerlandpoulikakos@ethz.ch

Thomas Brunschwiler, Bruno Michel

Advanced Thermal Packaging, IBM Zurich Research Laboratory, IBM Research GmbH, 8803 Rueschlikon, Switzerland

J. Heat Transfer 132(12), 121402 (Sep 22, 2010) (9 pages) doi:10.1115/1.4002287 History: Received February 09, 2010; Revised July 21, 2010; Published September 22, 2010; Online September 22, 2010

## Abstract

New generation supercomputers with three dimensional stacked chip architectures pose a major challenge with respect to the removal of dissipated heat, which can reach currently as high as $250 W/cm2$ in multilayer chip stacks of less than $0.3 cm3$ volume. Interlayer integrated water cooling is a very promising approach for such high heat flux removal due to much larger thermal capacity and conductivity of water compared with air, the traditional cooling fluid. In the current work, a multiscale conjugate heat transfer model is developed for integrated water cooling of chip layers and validated with experimental measurements on an especially designed thermal test vehicle that simulates a four tier chip stack with a footprint of $1 cm2$. The cooling heat transfer structure, which consists of microchannels with cylindrical pin-fins, is conceived in such a way that it can be directly integrated with the device layout in multilayer chips. Every composite layer is cooled by water flow in microchannels (height of $100 μm$), which are arranged in two port water inlet-outlet configuration. The total power removed in the stack is 390 W at a temperature gradient budget of 60 K from liquid inlet to maximal junction temperature, corresponding to about $1.3 kW/cm3$ volumetric heat flow. The computational cost and complexity of detailed computational fluid dynamics (CFD) modeling of heat transfer in stacked chips with integrated cooling can be prohibitive. Therefore, the heat transfer structure is modeled using a porous medium approach, where the model parameters of heat transfer and hydrodynamic resistance are derived from averaging the results of the detailed 3D-CFD simulations of a single streamwise row of fins. The modeling results indicate that an isotropic porous medium model does not accurately predict the measured temperature fields. The variation of material properties due to temperature gradients is found to be large; therefore, variable properties are used in the model. It is also shown that the modeling of the heat transfer in the cooling sublayers requires the implementation of a porous medium approach with a local thermal nonequilibrium, as well as orthotropic heat conduction and hydrodynamic resistance. The improved model reproduces the temperatures measured in the stack within 10%. The model is used to predict the behavior of multilayer stacks mimicking the change of heat fluxes resulting from variations in the computational load of the chips during their operation.

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Copyright © 2010 by American Society of Mechanical Engineers
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## Figures

Figure 1

Cross section of the pyramid chip stack in transversal direction

Figure 2

Detailed schematic of the experimental setup

Figure 3

Geometry with 20 inline pins simulated using detailed 3D conjugate heat transfer model and a zoom in into a single cell (pin-fin and fluid)

Figure 4

Cross section of the CFD model in streamwise direction

Figure 5

CFD model of a two-port multilayer stack of chip

Figure 6

Pressure drop as a function of the average cell velocity for different plate heat fluxes

Figure 7

Comparison between simulated and fitted pressure drop

Figure 8

Total local Nusselt number for different mass flow rates and Q̇″=25 W/cm2

Figure 9

Comparison between simulated and fitted Nusselt number

Figure 10

Validation of the porous medium model with measurements for 4 hot-spots operating in the “top” layer

Figure 11

Validation of the porous medium model with measurements for three hot-spots operating on the top of each other

Figure 12

Impact of constant and variable material properties on temperature rise at benchmark operation condition in different chip levels

Figure 13

Comparison of equilibrium and nonequilibrium model at benchmark operating chip

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