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Research Papers: Two-Phase Flow and Heat Transfer

Pool Boiling Heat Transfer and Bubble Dynamics Over Plain and Enhanced Microchannels

[+] Author and Article Information
Dwight Cooke

Department of Mechanical Engineering, Kate Gleason College of Engineering, Rochester Institute of Technology, Rochester, NY 14623-5698

Satish G. Kandlikar1

Department of Mechanical Engineering, Kate Gleason College of Engineering, Rochester Institute of Technology, Rochester, NY 14623-5698sgkeme@rit.edu

1

Corresponding author.

J. Heat Transfer 133(5), 052902 (Feb 03, 2011) (9 pages) doi:10.1115/1.4003046 History: Received May 28, 2010; Revised November 11, 2010; Published February 03, 2011; Online February 03, 2011

Pool boiling is of interest in high heat flux applications because of its potential for removing large amount of heat resulting from the latent heat of evaporation and little pressure drop penalty for circulating coolant through the system. However, the heat transfer performance of pool boiling systems is not adequate to match the cooling ability provided by enhanced microchannels operating under single-phase conditions. The objective of this work is to evaluate the pool boiling performance of structured surface features etched on a silicon chip. The performance is normalized with respect to a plain chip. This investigation also focuses on the bubble dynamics on plain and structured microchannel surfaces under various heat fluxes in an effort to understand the underlying heat transfer mechanism. It was determined that surface modifications to silicon chips can improve the heat transfer coefficient by a factor up to 3.4 times the performance of a plain chip. Surfaces with microchannels have shown to be efficient for boiling heat transfer by allowing liquid to flow through the open channels and wet the heat transfer surface while vapor is generated. This work is expected to lead to improved enhancement features for extending the pool boiling option to meet the high heat flux removal demands in electronic cooling applications.

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Copyright © 2011 by American Society of Mechanical Engineers
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References

Figures

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Figure 4

(a)–(e) Surface images of chips used at 20x magnification and (f) example of a 250 μm deep channel cross section taken from Ref. 21

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Figure 9

Boiling curves from Ref. 22 for FC-72 with the heat flux normalized to the surface area

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Figure 10

Successive images of bubble nucleation on chip C at 1 ms intervals

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Figure 5

Boiling curves for chips A–F listed in Table 1 based on projected base area

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Figure 1

Schematic of boiling test fixture (a) cartridge heater, (b) copper heating block (c) insulating block, (d) silicon test chip, (e) gasket, (f) polycarbonate visualization tube, (g) high speed camera, (h) auxiliary heater, (i) compression screws, (j) compression screws, and (k) data acquisition with 4 K-type thermocouples

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Figure 2

(a) Schematic of copper chip setup for contact resistance calculations (not to scale) (b) equivalent thermal circuit for 1D heat conduction analysis

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Figure 3

Example of etched silicon chip with heated area boxed

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Figure 6

Boiling curves for chip C when decreasing the heat flux then increasing the heat flux showing no hysteresis effects

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Figure 7

Boiling curve for each of the chips tested with the heat flux normalized to the surface area

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Figure 8

Boiling curves from Ref. 22 for FC-72 on various surfaces

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Figure 11

Successive images at 2 ms intervals of boiling at high heat fluxes for chips B (a)-(d) and F (e)-(h)

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Figure 12

Proposed mechanism of bubble dynamics on a microchannel surface (not to scale)

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