Research Papers

Reduced Order Thermal Models of Multiscale Microsystems

[+] Author and Article Information
Yogendra Joshi

 G.W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332 yogendra.joshi@me.gatech.edu

J. Heat Transfer 134(3), 031008 (Jan 13, 2012) (11 pages) doi:10.1115/1.4005150 History: Received August 25, 2010; Revised May 23, 2011; Published January 13, 2012; Online January 13, 2012

Thermal systems often involve multiple spatial and temporal scales, where transport information from one scale is relevant at others. Optimized thermal design of such systems and their control require approaches for their rapid simulation. These activities are of increasing significance due to the need for energy efficiency in the operation of these systems. Traditional full-field simulation methodologies are typically unable to resolve these scales in a computationally efficient manner. We summarize recent work on simulations of conjugate transport processes over multiple length scales via reduced order modeling through approaches such as compact finite elements and proper orthogonal decomposition. In order to incorporate the influence of length scales beyond those explicitly considered, lumped models are invoked, with appropriate handshaking between the two frameworks. We illustrate the methodology through selected examples, with a focus on information technology systems.

Copyright © 2012 by American Society of Mechanical Engineers
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Figure 17

Total cooling energy consumption of adaptable and traditional designs for 9 years [50]. Cross signs show that the reliability requirement is violated, i.e., Tmax  > 32 °C, by the traditional design at years# 3, 7, 8, and 9.

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Figure 1

Eight decades of length scales in information technology systems, from on-chip interconnects to data centers (figure not to scale)

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Figure 2

Modeling taxonomy (adapted from Ref. [1])

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Figure 3

Schematic of interconnect stack with metal lines and vias [16]

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Figure 4

A conventional element and a compact element which have shaded metallic regions together with dielectric regions are shown at bottom. The interpolating function for node 1 in both approaches is shown above. In the compact element case, this function ignores temperature drop across the metallic region [16].

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Figure 5

A set of uniformly spaced interconnects embedded in the dielectric is shown on the top. Percentage error in FEM and CM when compared with detailed finite element simulations is shown [16].

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Figure 6

A schematic of the long chain of interconnects and vias is shown on the left and temperature rise map of the heat-generating region in degree Celsius, for a current density of 23.8 MA/cm2 is shown on the right [16]

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Figure 7

Multiscale thermal modeling: bridging the gap between system and board/component modeling [26]

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Figure 8

Computational domain for system level modeling (all dimensions in cm) [26]

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Figure 9

PQFP and the detailed dimension for component level modeling (all dimensions in mm) [26]

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Figure 10

Multiscale reduced order modeling methodology for interconnected domains [41]

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Figure 11

(a) Simulated rack [41]: experimental model (left), numerical model (right) (b) system flow resistance network

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Figure 12

Comparison of CFD and FNM-POD simulation results for temperature distribution across chips and FR4 board at system level for simulated rack [41]: (a) Server4, and (b) Server5

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Figure 13

Typical air-cooled data center with raised floor plenum

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Figure 14

Case study data center cell [45] top view; dimensions in m. Only one quarter of the cell is shown due to symmetry.

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Figure 15

Contours of (a) CFD/HT temperature, (b) POD temperature, and (c) relative error (°C) at rack inlets for test case of 3 m/s, 27 kW, 7 kW, 13 kW, 24 kW [45]

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Figure 16

Adaptable robust design in energy efficient data centers [50]



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