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Electronic Cooling

Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors

[+] Author and Article Information
Man Prakash Gupta

 G. W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332mp.gupta@gatech.edu

Minki Cho, Saibal Mukhopadhyay

 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta GA, 30332mcho8@gatech.edu

Satish Kumar

 G. W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332satish.kumar@me.gatech.edu

J. Heat Transfer 134(6), 061401 (May 02, 2012) (8 pages) doi:10.1115/1.4006012 History: Received January 20, 2011; Revised October 24, 2011; Published April 30, 2012; Online May 02, 2012

In this paper, a proactive thermal management technique called “power multiplexing” is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called “proximity index” which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing.

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Copyright © 2012 by American Society of Mechanical Engineers
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Figures

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Figure 1

(a) Flow tunnel with a heat sink and an electronic package used for the thermal modeling. (b) Schematic of the heat sink and electronic package of the multicore processor which includes heat spreader, TIM, chip, and substrate (view along the direction of inlet flow).

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Figure 2

Effect of timeslice variation on (a) peak temperature and (b) spatial temperature difference for random multiplexing. The top and bottom curves in both figures correspond to no multiplexing and uniform power, respectively. 25% cores are considered to be active with total power = 128 W.

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Figure 3

Thermal profile on 256 core chip at time instant, t/τ = 6.6, for (a) no multiplexing, (b) multiplexing with timeslice = 0.033τ, and (c) multiplexing with timeslice = 0.0033τ using random core migration policy. 25% active cores with total power = 128 W.

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Figure 4

Effect of timeslice variation on (a) peak temperature and (b) spatial temperature difference for cyclic multiplexing. 25% cores are considered to be active with total power = 128 W.

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Figure 5

Thermal profile on a chip for cyclic policy at t = 6.6τ for (a) timeslice = 0.0033τ, (b) timeslice = 0.033τ, and (c) no change in configuration. Higher spatial thermal uniformity can be observed for high frequency of multiplexing. 25% active cores with total power = 128 W.

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Figure 6

Effect of timeslice variation on (a) peak temperature and (b) spatial temperature difference for global multiplexing. 25% cores are considered to be active with total power = 128 W.

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Figure 7

Thermal profile on a chip for global coolest replace policy at t/τ = 6.6 for (a) no multiplexing, (b) timeslice = 0.33τ, and (c) timeslice = 0.033τ. Significant improvement in the uniformity of the thermal profile can be observed from case (a) to case (b). 25% active cores with total power = 128 W.

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Figure 8

Effect of variation in number of swapped cores (N) on (a) peak temperature and (b) spatial temperature difference for global multiplexing. 25% cores are considered to be active with total power = 128 W.

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Figure 9

Comparison of the effect of different migration policies on (a) peak temperature and (b) spatial temperature difference. Timeslice is kept as 0.033τ during power multiplexing. 25% cores are considered to be active with total power = 128 W.

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Figure 10

Thermal profile on a chip at t/τ = 6.6 for (a) random policy, (b) checkerboard, (c) global coolest replace. Timeslice is taken as 0.033τ for all cases. Very high spatial thermal uniformity can be seen for the global multiplexing. 25% active cores with total power = 128 W.

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Figure 11

Variation of peak temperature with proximity index under steady state conditions. Each point in the plot corresponds to a unique power configuration. 25% cores are considered to be active with total power = 128 W.

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Figure 12

Variation of normalized Performance Improvement with no multiplexing, slow (timeslice = 0.33τ), medium (timeslice = 0.033τ) and fast (timeslice = 0.0033τ) multiplexing

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