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Research Papers: Electronic Cooling

# Investigation of Hierarchically Branched-Microchannel Coolers Fabricated by Deep Reactive Ion Etching for Electronics Cooling Applications

[+] Author and Article Information
J. P. Calame1

Electronics Science and Technology Division, Naval Research Laboratory, Washington, DC 20375jeffrey.calame@nrl.navy.mil

D. Park, R. Bass

Electronics Science and Technology Division, Naval Research Laboratory, Washington, DC 20375

R. E. Myers

ATK Mission Research, Newington, VA 22122

P. N. Safier

S&J Solutions LLC, Alexandria, VA 22314

1

Corresponding author. Present address: Naval Research Laboratory, Code 6843, 4555 Overlook Ave. SW, Washington, DC 20375.

J. Heat Transfer 131(5), 051401 (Mar 20, 2009) (9 pages) doi:10.1115/1.3001017 History: Received April 16, 2008; Revised September 10, 2008; Published March 20, 2009

## Abstract

The removal of high heat fluxes from BeO ceramic and GaN-on-SiC semiconductor dies using hierarchically branched-microchannel coolers is investigated, in order to examine the impact of the number of branching levels on performance. The microchannel coolers are made by lithography and deep reactive ion etching of single crystal silicon. The test dies contain a dc-operated resistive zone that approximates the spatially averaged heat flux that would appear in low-temperature cofired ceramic microwave circuit packages and in monolithic microwave integrated circuits. For the particular geometric constraints selected for the study (three source/exhaust channels, $∼5×5 mm2$ die footprint, $200 μm$ deep channels in a $400 μm$ thick silicon wafer), the optimum performance is achieved with three hierarchical levels of branched-channel size. A heat flux of $1.5 kW/cm2$ is removed from the $3.6×4.7 mm2$ resistive zone of the BeO-based die, at a surface temperature of $203°C$. When attached instead to a high thermal conductivity GaN-on-SiC die with a $1.2×5 mm2$ resistive zone, a heat flux of $3.9 kW/cm2$ is removed from the resistive zone at $198°C$ surface temperature. The total water flow rate is 275 ml/min in both situations. The experimental results are found to be in reasonable agreement with finite element simulations based on idealized estimates of convection coefficients within the channels. For the three-channel size configuration, an effective heat transfer coefficient in the range of $12.2–13.4 W/cm2 K$ (with respect to a $20°C$ bulk fluid temperature) is inferred to be present on the top of the microchannel cooler, based on simulations and derived values obtained from the experimental data.

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## Figures

Figure 1

(a) Schematic showing the conceptual evolution of a hierarchically branched cooling channel network, obtained by adding successive levels of cross channels to an initial network of parallel channels; (b) illustration of the assembly of a hierarchically branched-microchannel cooler by placing a slab containing the channels onto a backing block; (c) top view of the completed test package showing a heat source testing die that is attached to the top surface of the microchannel cooler

Figure 2

Optical micrographs of the family of hierarchically branched-microchannel coolers made by DRIE showing the undersides of the central region of the etched silicon slabs. Shown are the (a) one-channel, (b) two-channel, (c) three-channel, and (d) four-channel size configurations. Scanning electron micrographs of the (e) three-channel and (f) four-channel size configurations are also provided.

Figure 3

(a) Photograph of a hierarchically branched-channel cooler with an attached BeO-based heat source die; (b) ANSYS simulation of temperatures in the three-channel size configuration at 1 kW/cm2 dissipation in the resistive zone; (c) experimental resistive zone temperature versus power dissipation data (symbols) and ANSYS simulations (lines) for the various channel configurations

Figure 4

Experimentally measured differential pressure versus flow data for the various channel configurations

Figure 5

(a) Map of the simulated temperatures present on the top silicon surface of the three-channel size hierarchically-branched cooler configuration (beneath the die footprint), when 1 kW/cm2 is being dissipated in the resistive zone of the overlying die; (b) corresponding map of simulated local heat transfer coefficients, and (c) plot of temperature and local heat transfer coefficient along the y-direction at two different x locations within these maps

Figure 6

(a) Plot of the average heat transfer coefficient (on the top of the silicon microchannel cooler surface, under the die footprint) as a function of the number of channel sizes in the configuration. Experiment-derived values are shown by the solid circle symbols/solid lines, along with ANSYS simulations using various averaging strategies and assuming turbulent conditions (in all channels except the smallest in the 4-channel configuration); (b) similar comparison between experiment-derived values and ANSYS simulations that are performed assuming FD and SD laminar conditions in all levels of cross channels (primary channels remain turbulent).

Figure 7

Experimentally measured GaN temperature versus power dissipation data (solid circles) for a GaN-on-SiC heat source die that is attached to the three-channel size hierarchically branched-channel cooler along with ANSYS simulations. A photograph of the package is shown in the inset.

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