Research Papers: Max Jakob Award Paper

Heat in Computers: Applied Heat Transfer in Information Technology

[+] Author and Article Information
Wataru Nakayama

ASME Life Fellow
ThermTech International,
920-7 Higashi Koiso, Oh-Iso Machi,
Kanagawa 255-0004, Japan
e-mail: watnakayama@aol.com

Contributed by the Heat Transfer Division of ASME for publication in the JOURNAL OF HEAT TRANSFER. Manuscript received July 30, 2013; final manuscript received August 25, 2013; published online October 21, 2013. Editor: Terrence W. Simon.

J. Heat Transfer 136(1), 013001 (Oct 21, 2013) (22 pages) Paper No: HT-13-1378; doi: 10.1115/1.4025377 History: Received July 30, 2013; Revised August 25, 2013

Since the advent of modern electronics technology, heat transfer science and engineering has served in the development of computer technology. The computer as an object of heat transfer research has a unique aspect; it undergoes morphological transitions and diversifications in step with the progress of microelectronics technology. Evolution of computer's hardware manifests itself in increasing packing density of electronic circuits, modularization of circuit assemblies, and increasing hierarchical levels of system internal structures. These features are produced by the confluence of various factors; the primary factors are the pursuit of ever higher processing performance, less spatial occupancy, and higher energy utilization efficiency. The cost constraint on manufacturing also plays a crucial role in the evolution of computer's hardware. Besides, the drive to make computers ubiquitous parts of our society generates diverse computational devices. Concomitant developments in heat generation density and heat transfer paths pose fresh challenges to thermal management. In an introductory part of the paper, I recollect our experiences in the mainframe computers of the 1980s, where the system's morphological transition allowed the adoption of water cooling. Then, generic interpretations of the hardware evolution are attempted, which include recapturing the past experience. Projection of the evolutionary trend points to shrinking space for coolant flow, the process commonly in progress in all classes of computers today. The demand for compact packaging will rise to an extreme level in supercomputers, and present the need to refocus our research on microchannel cooling. Increasing complexity of coolant flow paths in small equipment poses a challenge to a user of computational fluid dynamics (CFD) simulation code. In highly integrated circuits the paths of electric current and heat become coupled, and coupled paths make the electrical/thermal codesign an extremely challenging task. These issues are illustrated using the examples of a consumer product, a printed circuit board (PCB), and a many-core processor chip.

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Fig. 1

Projection of heat flux on VLSI chips as compared with other high-heat-flux data; the projection made in the mid-1980s [6]

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Fig. 2

Heat load on chips, modules, and printed wiring boards; the data from the Japanese mainframe and supercomputers of the period 1970s–1980s. (Solid symbol = indirect water-cooled machine, open symbol = air-cooled machine) [7]

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Fig. 3

Schematics of air-cooled and water-cooled computers

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Fig. 4

Printed wiring board used in Hitachi's last generation of air-cooled mainframe computer, M680 (announced in 1985) [10]

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Fig. 5

A CPU composed of multichip modules on a large mother board (right), and an indirect water-cooled multichip module (left) (Hitachi M880) [11]

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Fig. 6

Boiling cooling of simulated chips, from the experiment conducted at Hitachi in the 1980s

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Fig. 7

Air-cooled CPU board in a server computer introduced in around 2006 (Fujitsu PRIMEPOWER2500) [24]

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Fig. 8

Hardware organization of the computer; the process involves stacking, modularization, and hierarchical assembling of components

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Fig. 9

Trade-offs between area (A), process time (T), and power consumption (P) on the basic computer model

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Fig. 10

Schematic floor plan of a multicore processor chip

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Fig. 11

A card-stack model of processing system. Circuit element A is connected to another element B on a different card by metal lines on the cards and an optical line in the side tile [47].

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Fig. 12

Graph of computing efficiency versus computing density. The data symbols show the state points of sample supercomputers. The data in the upper right corner are for a BE model [47].

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Fig. 13

Coolant path spacing (df) versus computing density. The coolant space has to be squeezed to let the state point of the card-stack model fall on the diagonal of Fig. 12 [47]. The data symbols: C is the model for CRAY 1, E for Earth Simulator, K for K-Computer, D for DARPA target, and BE for brain equivalent.

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Fig. 14

Illustration of the inside of portable projection display equipment; a PCB caps the optical assembly, but shown here in lifted-up view. Arrows show airflow vectors

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Fig. 15

Airflow in a space under the PCB [59]

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Fig. 16

A PCB in JEDEC test environment: Zone A is the surface area of the PCB exposed to the air, zone B is where electrical interconnects between the package and the PCB are provided, and in zone C the package and the PCB are separated by thin air space. The vias and the copper plates in zone B, and heat flow vectors are shown in an expanded sketch [60].

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Fig. 17

Hierarchical layout of active and background cells on a simulated multicore processor die. The dimensions are used in the case studies; the die footprint is 20 mm × 20 mm, the target spot of temperature calculation is at 13.3 mm from the corner of the die in both the horizontal and vertical directions [71].

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Fig. 18

Temperatures of the focal cell (θHS,k) and the background cell at the corner edge of the die (θmin), and their difference denoted as the temperature contrast (ΔθHS,k). The case corresponds to a die cooled by a high-performance air-cooled heat sink. The power distribution ratios are set as rp0 = 0.3, rpk = 0 for k ≥ 1. The spatial resolution level indexes are also shown. The horizontal axis is the normalized cell length [71].

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Fig. 19

The ratio of heat flow from the focal cell to the wiring layer (QU,k) to level-k heat input (Qe,k). The horizontal axis is the normalized cell length. The case corresponds to a die cooled by a high-performance air-cooled heat sink. The curve Ref is for the reference structure shown in the inset. For Bulk, the SiO2 layer is removed. For No Wire, the metals in the wiring layer are ignored [71].

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Fig. 20

Metal elements in the wiring layer on a VLSI chip: a picture taken by a scanning electron microscope. (Courtesy of Dr. E. Ibe, Production Engineering Laboratory, Hitachi, Ltd.)




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