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Research Papers

Thermal Analysis of AlGaN/GaN HEMTs Using Angular Fourier-Series Expansion

[+] Author and Article Information
Dubravko I. Babić

Faculty of Electrical Engineering
and Computing,
University of Zagreb,
Zagreb, Croatia;
Group4 Labs, Inc.,
3485 Edison Way, Menlo Park, CA 94035
e-mail: dubravko.babic@group4labs.com

Contributed by the Heat Transfer Division of ASME for publication in the Journal of Heat Transfer. Manuscript received December 19, 2011; final manuscript received November 6, 2012; published online September 23, 2013. Assoc. Editor: Sujoy Kumar Saha.

J. Heat Transfer 135(11), 111001 (Sep 23, 2013) (9 pages) Paper No: HT-11-1580; doi: 10.1115/1.4024594 History: Received December 19, 2011; Revised November 06, 2012

Thermal analysis of planar and near-square semiconductor device chips employing angular Fourier-series (AFS) expansion is presented for the first time. The determination of the device peak temperature using AFS requires only a single two-dimensional computation, while full three-dimensional temperature distribution can be obtained, if desired, by successively adding higher-order Fourier terms, each of which requires a separate 2D computation. The AFS method is used to compare the heat spreading characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) fabricated on silicon, silicon carbide, and synthetic diamond. We show that AlGaN/GaN HEMTs built using GaN/diamond technology can offer better than half the thermal resistance of GaN/SiC HEMTs under worst-case cooling conditions. Furthermore, we show that, if left unmanaged, an inherent and non-negligible thermal boundary resistance due to the integration of semiconductor epilayers with non-native substrates will dampen the benefits of highly conductive substrates such as SiC and diamond.

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Figures

Grahic Jump Location
Fig. 1

Epilayer designs of the HEMTs modeled in this work. The bold line indicates the location of the heat source (not the shape). Figure is not to scale; the chip width of practical transistors is many times larger than the chip thickness.

Grahic Jump Location
Fig. 2

Schematic of an electronic device chip with heat dissipation (the left dashed side indicates the symmetry). The temperature at the hottest spot in the structure is denoted with TP, the bottom center and edge of the chip TC and the bottom edge of the chip TB, respectively. The convection cooling below the chip is specified with the heat transfer coefficient h.

Grahic Jump Location
Fig. 3

Grid-point numbering: temperature is given at the grid points—the intersections between grid lines (i, j), heat fluxes are given at halfway distances between grid points, and the power generation and thermal conductivity is specified in the areas enclosed by adjacent grid lines—grid “elements” (i, j).

Grahic Jump Location
Fig. 4

Types of intersection between a circle and a square and the associated parameters

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Fig. 5

Temperature and thermal conductivity profile at the origin of the coordinate system for device C

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Fig. 6

Calculation times for a single-gate HEMT performed with AFS and conventional TDF thermal analysis (device A-II)

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Fig. 7

Normalized thermal conductance for epi designs A, B, and C with heat source shape III

Grahic Jump Location
Fig. 8

Thermal resistance of structures A, B, and C′ as function of heat transfer coefficient (left axis). The solid symbols show TPTB, while the empty symbols show TC − TB. Right axis show the ratio of thermal resistance of GaN/SiC and GaN/Si devices divided by the thermal resistance of GaN/Diamond device.

Grahic Jump Location
Fig. 9

Thermal resistance under isoflux cooling versus diamond thermal conductivity for heat source III

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