The semiconductor industry, following Moore's law, has consistently followed a trajectory of miniaturization that enables design engineers to achieve greater levels of innovation in the same or smaller die footprints. According to Samsung technologists, the next generation of semiconductor technology will cost about $10 billion to create. Alternatively, improved performance through lowering of signal delays can also be achieved using stacked or 3D packaging. With this architectural achievement come cooling challenges as it is difficult to utilize conventional cooling technology and especially when stacking logic and memory processors for high end applications. The accumulation of excessive heat within the stack is a challenge that has caused thermal engineers to focus on the issue of extracting this heat from the system. Thus, one important aspect of design is the ability to obtain an accurate analytical temperature solution of the multilayer stack packages beforehand in order to sustain the reliability of the 3D stack packages albeit for a more simplified configuration. This study addresses the analytical solution of temperature distribution in multilayer bodies by using the Mathematica code developed in this study. The numerical approach using ansys Workbench is discussed, and the results are compared with the one obtained analytically.