Research Papers: Max Jakob Award Paper

Heat in Computers: Applied Heat Transfer in Information Technology

[+] Author and Article Information
Wataru Nakayama

ASME Life Fellow
ThermTech International,
920-7 Higashi Koiso, Oh-Iso Machi,
Kanagawa 255-0004, Japan
e-mail: watnakayama@aol.com

Contributed by the Heat Transfer Division of ASME for publication in the JOURNAL OF HEAT TRANSFER. Manuscript received July 30, 2013; final manuscript received August 25, 2013; published online October 21, 2013. Editor: Terrence W. Simon.

J. Heat Transfer 136(1), 013001 (Oct 21, 2013) (22 pages) Paper No: HT-13-1378; doi: 10.1115/1.4025377 History: Received July 30, 2013; Revised August 25, 2013

Since the advent of modern electronics technology, heat transfer science and engineering has served in the development of computer technology. The computer as an object of heat transfer research has a unique aspect; it undergoes morphological transitions and diversifications in step with the progress of microelectronics technology. Evolution of computer's hardware manifests itself in increasing packing density of electronic circuits, modularization of circuit assemblies, and increasing hierarchical levels of system internal structures. These features are produced by the confluence of various factors; the primary factors are the pursuit of ever higher processing performance, less spatial occupancy, and higher energy utilization efficiency. The cost constraint on manufacturing also plays a crucial role in the evolution of computer's hardware. Besides, the drive to make computers ubiquitous parts of our society generates diverse computational devices. Concomitant developments in heat generation density and heat transfer paths pose fresh challenges to thermal management. In an introductory part of the paper, I recollect our experiences in the mainframe computers of the 1980s, where the system's morphological transition allowed the adoption of water cooling. Then, generic interpretations of the hardware evolution are attempted, which include recapturing the past experience. Projection of the evolutionary trend points to shrinking space for coolant flow, the process commonly in progress in all classes of computers today. The demand for compact packaging will rise to an extreme level in supercomputers, and present the need to refocus our research on microchannel cooling. Increasing complexity of coolant flow paths in small equipment poses a challenge to a user of computational fluid dynamics (CFD) simulation code. In highly integrated circuits the paths of electric current and heat become coupled, and coupled paths make the electrical/thermal codesign an extremely challenging task. These issues are illustrated using the examples of a consumer product, a printed circuit board (PCB), and a many-core processor chip.

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Moore, G., 1965, “Cramming More Components Onto Integrated Circuits,” Electronics Mag., 38(8), pp. 114–117.
Schmidt, R., and Iyenger, M., 2008, “Information Technology Energy Usage and Our Planet,” Proc. ITHERM 08, May 28–31, Orlando, FL, pp. 1255–1275.
Sharma, R. K., Bash, C. E., Patel, C. D., Friedrich, R. J., and Chase, J. S., 2005, “Balance of Power: Dynamic Thermal Management for Internet Data Centers,” IEEE Internet Comput., 9(1), pp. 42–49. [CrossRef]
Nakayama, W., 2013, “The Heat Transfer Society of Japan, the Fiftieth Anniversary: Retrospect and Prospect,” Heat Transfer Eng., 24(4), pp. 409–419. [CrossRef]
A.Bar-Cohen ed., Encyclopedia of Thermal Packaging, 2013, World Scientific, Singapore.
Oktay, S., Hannemann, R., and Bar-Cohen, A., 1986, “High Heat From a Small Package,” ASME Mech. Eng., 108(3) pp. 36–42.
Nakayama, W., 1992, “Japanese Supercomputers in Thermal Perspective,”High Performance Computing, Research and Practice in Japan, R.Mendez, ed., John Wiley & Sons, Chichester, UK, pp. 55–73.
Bergles, A., 1986, “Evolution of Cooling Technology for Electrical, Electronic, and Microelectronic Equipment,” Heat Transfer Eng., 7(3–4) pp. 97–106. [CrossRef]
Nakayama, W., and Bergles, A. E., 1990, “Cooling Electronic Equipment; Past, Present, and Future,” Heat Transfer in Electronic and Microelectronic Equipment, A. E.Bergles ed., Hemisphere Publishing Corporation, New York, pp. 3–39.
Kodaka, T., Wakai, M., Hashimoto, T., Ogawa, K., Wada, K., and Sakamoto, M., 1985, “Processing Scheme of M-680/682H With Enhanced High-Speed Performance by Means of ALU Pipelines and Hierarchical Memories,” Nikkei Electronics, November issue, pp. 228–288.
Kobayashi, F., Watanabe, Y., Yamamoto, M., Anzai, A., Takahashi, A., Daikoku, T., and Fujita, T., 1991, “Hardware Technology for HITACHI M-880 Processor Group,” Proceedings of 41st Electronic Components and Technology Conference, pp. 693–703.
Ashiwake, N., Daikoku, T., Kawamura, K., and Zushi, S., 1991, “A Flexible Thermal Contactor for the Cooling of Electronic Components,” Proceedings of ASME/JSME Thermal Engineering Joint Conference, March 17–22, Reno, NV, pp. 357–364.
Chu, R. C., Hwang, U. P., and Simons, R. E., 1982, “Conduction Cooling for an LSI Package: A One-Dimensional Approach,” IBM J. Res. Develop., 26, pp. 45–54. [CrossRef]
Nakayama, W., 1986, “Thermal Management of Electronic Equipment: A Review of Technology and Research Topics,” Appl. Mech. Rev., 39(12), pp. 1847–1868. [CrossRef]
Nakayama, W., Matsushima, H., and Goel, P., 1988, “Forced Convective Heat Transfer From Arrays of Finned Packages,” Cooling Technology for Electronic Equipment, W.Aung, ed., Hemisphere Publishing Corporation, New York, pp. 195–210.
Nakayama, W., and Bergles, A. E., 2003, “Thermal Interfacing Techniques for Electronic Equipment—A Perspective,” ASME J. Electron. Packag., 125(2), Special Issue in Honor of Dr. M. M. Yovanovich, pp. 192–199. [CrossRef]
Nakayama, W., Nakajima, T., and Hirasawa, S., 1984, “Heat Sink Studs Having Enhanced Boiling Surfaces for Cooling of Microelectronic Components,” 1984 ASME Winter Annual Meeting, New Orleans, Dec. 9–14, ASME Paper No.84-WA/HT-89.
Nakayama, W., Daikoku, T., Kuwahara, H., and Nakajima, T., 1980, “Dynamic Model of Enhanced Boiling Heat Transfer on Porous Surfaces, Part I: Experimental Investigation,” ASME J. Heat Transfer, 102(3), pp. 445–450. [CrossRef]
Nakayama, W., Daikoku, T., Kuwahara, H., and Nakajima, T., 1980, “Dynamic Model of Enhanced Boiling Heat Transfer on Porous Surfaces, Part II: Analytical Modeling,” ASME J. Heat Transfer, 102(3), pp. 451–456. [CrossRef]
Nakayama, W., Daikoku, T., and Nakajima, T., 1982, “Effects of Pore Diameters and System Pressure on Nucleate Boiling Heat Transfer From Porous Surfaces,” ASME J. Heat Transfer, 104(2), pp. 286–291. [CrossRef]
Tuckerman, D. B., and Pease, R. F. W., 1981, “High-Performance Heat Sink for VLSI,” IEEE Electron Device Lett., 2, pp. 126–129. [CrossRef]
Keyes, R. W., 2001, “Fundamental Limits of Silicon Technology,” Proc. IEEE, 89(3), pp. 227–239. [CrossRef]
Morris, J. E., and Tummala, R. R., 2001, “The Role of Packaging in Microelectronics,” Fundamentals of Microsystems Packaging, R. R.Tummala ed., McGraw-Hill, New York, Chapter 2.
Wei, J., 2008, “Challenges in Cooling Design of CPU Packages for High-Performance Servers,” Heat Transfer Eng., 29(2), pp. 178–187. [CrossRef]
Kobayashi, F., Watanabe, Y., Kasai, K., Koide, K., Nakanishi, K., and Sato, R., 2000, “Hardware Technology for the HITACHI MP5800 Series (HDS Skyline Series),” IEEE Trans. Adv. Packag., 23(3), pp. 504–514. [CrossRef]
Ramaswamy, C., Joshi, Y., Nakayama, W., and Johnson, W., 2000, “Thermal Performance of a Combined Effects of Sub-Cooling and Operating Pressure of a Two-Chamber Thermosyphon,” IEEE Trans. Compon. Packag. Technol., 23(1) pp. 61–69. [CrossRef]
Borkar, S., 2007, “Thousand Core Chips—A Technology Perspective,” IEEE Design Automation Conference (DAC 2007), pp. 746–749.
Flynn, M. J., and Hung, P., 2005, “Microprocessor Design Issues: Thoughts on the Road Ahead,” IEEE Micro, 25(3), pp. 16–31. [CrossRef]
Jisso Technology Roadmap, 2007, Japan Electronic Industry Technology Association.
Danielson, R. D., Krajewski, N., and Brost, J., 1986, “Cooling a Superfast Computer,” Electronic Packaging and Production, pp. 44–45.
Danielson, R. D., Tousignant, L., and Bar-Cohen, A., 1987, “Saturated Pool Boiling Characteristics of Commercially Available Perfluorinated Liquids,” Proceedings of ASME/JSME Thermal Engineering Joint Conference, Vol. 3, ASME, pp. 419–430.
Incropera, F. P., and DeWitt, D. P., 1996, Fundamentals of Heat and Mass Transfer, 4th ed., John Wiley & Sons, New York, p. 450.
Leavitt, N., 2012, “Big Iron Moves Toward Exascale Computing,” IEEE Comput., 45(11), pp. 14–17. [CrossRef]
Kogge, P., 2011, “The Tops in Flops,” IEEE Spectrum, 48(2), p. 44–54. [CrossRef]
Koo, J-M., ImS., Jiang, L., and Goodson, K. E., 2005, “Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures,” ASME J. Heat Transfer, 127, pp. 49–58. [CrossRef]
Brunschwiler, T., Paredes, S., Drechsler, U., Michel, B., Cesar, W., Leblebici, Y., Wunderle, B., and Reichl, H., 2010, “Heat-Removal Performance Scaling of Interlayer Cooled Chip Stacks,” Proceedings of ITHERM 10, June 2–5, Las Vegas, NV, pp. 1–12.
Dang, B., Bakir, M. S., Sekar, D. C., King, C. R., and Meindl, D., 2010, “Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips,” IEEE Trans. Adv. Packag., 33(1), pp. 79–87. [CrossRef]
Emma, P. G., and Kursun, E., 2008, “Is 3D Chip Technology the Next Growth Engine for Performance Improvement?,” IBM J. Res. Dev., 52(6), pp. 541–552. [CrossRef]
Kishimoto, T., and Ohsaki, T., 1986, “VLSI Packaging Technique Using Liquid-Cooled Channels,” IEEE Trans. Compon., Hybrids, Manuf. Technol., 9(4), pp. 328–335. [CrossRef]
Ozaktas, H. M., and Goodman, J. W., 1992, “Implications of Interconnection Theory for Optical Digital Computing,” Appl. Opt., 31(26), pp. 5559–5567. [CrossRef] [PubMed]
Ozaktas, H. M., and Goodman, J. W., 1993, “Comparison of Local and Global Computation and Its Implications for the Role of Optical Interconnections in Future Nanoelectronic Systems,” Opt. Commun., 100(1–4), pp. 247–258. [CrossRef]
Ozaktas, H. M., Oksuzoglu, Pease, R. F. W., and Goodman, J. P., 1992, “Effect on Scaling of Heat Removal Requirements in Three-Dimensional Systems,” Int. J. Electron., 73(6), pp. 1227–1232. [CrossRef]
Nakayama, W., 1990, “On the Accommodation of Coolant Flow Paths in High-Density Packaging,” IEEE Trans. Compon., Hybrids, Manuf. Technol., 13(4), pp. 1040–1049. [CrossRef]
Nakayama, W., 1994, “Information Processing and Heat Transfer Engineering: Some Generic Views on Future Research Needs,” Cooling of Electronic Systems, S.Kakac, H.Yuncu, and K.Hijikata, eds., Kluwer Academic Publishers, Dordrecht, The Netherlands, pp. 911–943.
Nakayama, W., 1993, “How to Sustain the Upswing of FLOPS in Supercomputers in the Future?—Morphological Considerations of Systems,” Computers and Computing in Heat Transfer Science and Engineerng, W.Nakayama and K. T.Yang, ed., CRC Press, Boca Raton, FL, pp. 425–443.
Nakayama, W., 2013, “A Card Stack Model to Elucidate Key Challenges in the Development of Future Generation Supercomputers,” IEEE Access, 1, pp. 436–448. [CrossRef]
Ruch, P., Brunschwiler, T., Escher, W., Paredes, S., and Michel, B., 2011, “Toward Five-Dimensional Scaling: How Density Improves Efficiency in Future Computers,” IBM J. Res. Dev., 55(5), pp. 15:1–15:13. [CrossRef]
Calame, J. P., Park, D., Bass, R., Myers, R. E., and Safier, P. N., 2009, “Investigation of Hierarchically Branched-Microchannel Coolers Fabricated by Deep Reactive Ion Etching for Electronic Cooling Applications,” ASME J. Heat Transfer, 131(9), p. 051401. [CrossRef]
Kim, Y.-J., Joshi, Y. K., Fedorov, A. G., Lee, Y.-J., and Lim, S.-K., 2010, “Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Cirucits With Nonuniform Heat Flux,” ASME J. Heat Transfer, 132(4), p. 041009. [CrossRef]
Alfieri, F., Tiwari, M. K., Zinovik, I., and Poulikakos, D., 2010, “3D Integrated Water Cooling of a Composite Multilayer Stack of Chips,” ASME J. Heat Transfer, 132(12), p. 121402. [CrossRef]
Lasance, C., 2008, “Ten Years of Boundary-Condition-Independent Compact Thermal Modeling of Electronic Parts: A Review,” Heat Transfer Eng., 29(2), pp. 149–168. [CrossRef]
Leoni, N., and Amon, C. H., 2000, “Bayesian Surrogates for Integrating Numerical, Analytical, and Experimental Data: Application to Inverse Heat Transfer in Wearable Computers,” IEEE Trans. Compon. Packag. Technol., 23(1), pp. 23–32. [CrossRef]
Joshi, Y., 2012, “Reduced Order Thermal Models of Multiscale Microsystems,” ASME J. Heat Transfer, 134(3), p. 031008. [CrossRef]
Murthy, J. Y., and Mathur, S. R., 2012, “Computational Heat Transfer in Complex Systems: A Review of Needs and Opportunities,” ASME J. Heat Transfer, 134(3), p. 031016. [CrossRef]
Aichlmayer, H. T., and Kulacki, F. A., 2006, “The Effective Thermal Conductivity of Saturated Porous Media,” Advances in Heat Transfer, Vol. 39, Elsevier/Academic Press, London, pp. 377–460.
Nakayama, W., 2001, “An Approach to Fast Thermal Design of Compact Electronic Systems: A JSME Project,” Proceedings of InterPACK, July, Kauai, HI, ASME Paper No. IPACK2001-15532.
Nakayama, W., Matsuki, R., Hacho, Y., and Yajima, K., 2004, “A New Role of CFD Simulation in Thermal Design of Compact Electronic Equipment: Application of Build-Up Approach to Thermal Analysis of a Benchmark Model,” ASME J. Electron. Packag., 126, pp. 440–448. [CrossRef]
Maguire, L., Nakayama, W., Behnia, M., and Kondo, Y., 2008, “A CFD Study on the Effect of Shrinking Box Size on Cooling Airflows in Compact Electronic Equipment—The Case of a Portable Projection Display Equipment,” Heat Transfer Eng., 29(2), pp. 188–197. [CrossRef]
Nakayama, W., 2008, “Heat Conduction in Printed Circuit Boards: A Mesoscale Modeling Approach,” ASME J. Electron. Packag., 130(4), p. 041106. [CrossRef]
1995, “Integrated Circuit Test Method, Environment Conditions: Natural Convection (Still Air),” EIA/JEDEC Standard 51-2, Electronic Industries Alliance.
Nakayama, W., Nakajima, T., Koike, H., and Matsuki, R., 2007, “Heat Conduction in Printed Circuit Boards—Part I; Overview and the Case of a JEDEC Test Board,” ASME/Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK ’07), July 8–12, Vancouver, British Columbia, Canada, Paper No. IPACK2007-33605.
Nakayama, W., Nakajima, T., Koike, H., and Matsuki, R., 2007, “Heat Conduction in Printed Circuit Boards—Part II; Small PCBs Connected to Large Thermal Mass at Their Edge,” ASME/Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK ’07), July 8–12, Vancouver, British Columbia, Canada, Paper No. IPACK2007-33606.
Nakayama, W., Koizumi, K., Fukue, T., Ishizuka, M., Nakajima, T., Koike, H., and Matsuki, R., 2009, “Thermal Characterization of High-Density Interconnects In the Form of Equivalent Thermal Conductivity,” Proceedings of ASME InterPACK ’09, July 19–23, 2009, San Francisco, CA, Paper IPACK2009-89086.
Nakayama, W., Koizumi, K., Fukue, T., Ishizuka, M., Nakajima, T., Koike, H., and Matsuki, R., 2010, “Thermal Characterization of High-Density Interconnects: A Methodology Tested on a Model Coupon,” ITHERM 10, June 2–5, Las Vegas, NV, Paper No. 2640.
Nakayama, W., 2013, “Heat Conduction in Mobile Electronic Equipment: Study on the Effects of Some Key Parameters on Heat Source Temperature Based on a Three-Layer Model,” ASME J. Electron. Packag., 135(3), p. 034501. [CrossRef]
Mahajan, R., Chiu, C.-P., and Chrysler, G., 2006, “Cooling a Microprocessor Chip,” Proc. IEEE, 94(8), pp. 1476–1486. [CrossRef]
Pedram, M., and Nazarian, S., 2006, “Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods,” Proc. IEEE, 94(8), pp. 1487–1501. [CrossRef]
Esmaelizadeh, H., Biem, E., Amant, R. S., Sankaralingam, K., and Burger, D., 2011, “Dark Silicon and the End of Multicore Scaling,” 38th International Symposium on Computer Architecture (ISCA’11), pp. 1–12.
Nakayama, W., 2013, “Study on Heat Conduction in a Simulated Multi-Core Processor Chip: Part I—Analytical Modeling,” ASME J. Electron. Packag., 135(2), p. 021002. [CrossRef]
Nakayama, W., 2013, “Study on Heat Conduction in a Simulated Multi-Core Processor Chip: Part II—Case Studies,” ASME J. Electron. Packag., 135(2), p. 021003. [CrossRef]
Rao, W., Yang, C., Karri, R., and Orailogu, A., 2011, “Toward Future Systems With Nanoscale Devices: Overcoming the Reliability Challenge,” IEEE Comput., 44(2), pp. 46–53. [CrossRef]


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Fig. 4

Printed wiring board used in Hitachi's last generation of air-cooled mainframe computer, M680 (announced in 1985) [10]

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Fig. 5

A CPU composed of multichip modules on a large mother board (right), and an indirect water-cooled multichip module (left) (Hitachi M880) [11]

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Fig. 3

Schematics of air-cooled and water-cooled computers

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Fig. 2

Heat load on chips, modules, and printed wiring boards; the data from the Japanese mainframe and supercomputers of the period 1970s–1980s. (Solid symbol = indirect water-cooled machine, open symbol = air-cooled machine) [7]

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Fig. 1

Projection of heat flux on VLSI chips as compared with other high-heat-flux data; the projection made in the mid-1980s [6]

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Fig. 6

Boiling cooling of simulated chips, from the experiment conducted at Hitachi in the 1980s

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Fig. 7

Air-cooled CPU board in a server computer introduced in around 2006 (Fujitsu PRIMEPOWER2500) [24]

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Fig. 8

Hardware organization of the computer; the process involves stacking, modularization, and hierarchical assembling of components

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Fig. 9

Trade-offs between area (A), process time (T), and power consumption (P) on the basic computer model

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Fig. 10

Schematic floor plan of a multicore processor chip

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Fig. 11

A card-stack model of processing system. Circuit element A is connected to another element B on a different card by metal lines on the cards and an optical line in the side tile [47].

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Fig. 12

Graph of computing efficiency versus computing density. The data symbols show the state points of sample supercomputers. The data in the upper right corner are for a BE model [47].

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Fig. 13

Coolant path spacing (df) versus computing density. The coolant space has to be squeezed to let the state point of the card-stack model fall on the diagonal of Fig. 12 [47]. The data symbols: C is the model for CRAY 1, E for Earth Simulator, K for K-Computer, D for DARPA target, and BE for brain equivalent.

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Fig. 15

Airflow in a space under the PCB [59]

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Fig. 14

Illustration of the inside of portable projection display equipment; a PCB caps the optical assembly, but shown here in lifted-up view. Arrows show airflow vectors

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Fig. 16

A PCB in JEDEC test environment: Zone A is the surface area of the PCB exposed to the air, zone B is where electrical interconnects between the package and the PCB are provided, and in zone C the package and the PCB are separated by thin air space. The vias and the copper plates in zone B, and heat flow vectors are shown in an expanded sketch [60].

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Fig. 17

Hierarchical layout of active and background cells on a simulated multicore processor die. The dimensions are used in the case studies; the die footprint is 20 mm × 20 mm, the target spot of temperature calculation is at 13.3 mm from the corner of the die in both the horizontal and vertical directions [71].

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Fig. 18

Temperatures of the focal cell (θHS,k) and the background cell at the corner edge of the die (θmin), and their difference denoted as the temperature contrast (ΔθHS,k). The case corresponds to a die cooled by a high-performance air-cooled heat sink. The power distribution ratios are set as rp0 = 0.3, rpk = 0 for k ≥ 1. The spatial resolution level indexes are also shown. The horizontal axis is the normalized cell length [71].

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Fig. 19

The ratio of heat flow from the focal cell to the wiring layer (QU,k) to level-k heat input (Qe,k). The horizontal axis is the normalized cell length. The case corresponds to a die cooled by a high-performance air-cooled heat sink. The curve Ref is for the reference structure shown in the inset. For Bulk, the SiO2 layer is removed. For No Wire, the metals in the wiring layer are ignored [71].

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Fig. 20

Metal elements in the wiring layer on a VLSI chip: a picture taken by a scanning electron microscope. (Courtesy of Dr. E. Ibe, Production Engineering Laboratory, Hitachi, Ltd.)



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