The sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, was performed in this work to investigate thermal characteristics along with fatigue reliability of a thin-profile fine-pitch ball grid array chip-scale package subjected to power cycling. The numerical model was calibrated using steady-state and power cycling experiments. Following the calibrated numerical model, different power cycling durations on the thermal characteristics and fatigue reliability of the solder joints were examined. Numerical results indicate that, compared with thermal cycling, power cycling requires many more cycles to achieve a stabilized plasticity index between test cycles. The fatigue reliability would therefore be greatly underestimated if only such an index of the first several cycles is followed in the predictions.
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March 2009
Research Papers
Influence of Power Cycling Durations on Thermal and Fatigue Reliability Characteristics of Board-Level Chip-Scale Packages
Tong Hong Wang,
Tong Hong Wang
Central Labs,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, Taiwan
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Chang-Chi Lee,
Chang-Chi Lee
Central Labs,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, Taiwan
Search for other works by this author on:
Yi-Shao Lai, Mem. ASME,
Yi-Shao Lai, Mem. ASME
Central Labs,
e-mail: yishao_lai@aseglobal.com
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, Taiwan
Search for other works by this author on:
Kuo-Yuan Lee
Kuo-Yuan Lee
Central Labs,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, Taiwan
Search for other works by this author on:
Tong Hong Wang
Central Labs,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, Taiwan
Chang-Chi Lee
Central Labs,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, Taiwan
Yi-Shao Lai, Mem. ASME
Central Labs,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, Taiwane-mail: yishao_lai@aseglobal.com
Kuo-Yuan Lee
Central Labs,
Advanced Semiconductor Engineering, Inc.
, 26 Chin 3rd Road, Nantze Export Processing Zone, Kaohsiung 811, TaiwanJ. Electron. Packag. Mar 2009, 131(1): 011001 (5 pages)
Published Online: February 11, 2009
Article history
Received:
August 23, 2007
Revised:
April 15, 2008
Published:
February 11, 2009
Citation
Wang, T. H., Lee, C., Lai, Y., and Lee, K. (February 11, 2009). "Influence of Power Cycling Durations on Thermal and Fatigue Reliability Characteristics of Board-Level Chip-Scale Packages." ASME. J. Electron. Packag. March 2009; 131(1): 011001. https://doi.org/10.1115/1.3068294
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