... to model voids nucleation during reflow process. The established model designed a reflow process possibly preventing underfill voiding. The reflow process was validated using systematic experiments designed on the theoretical study with a commercial high I/O counts (5000>), fine-pitch (<150 μm) flip...

... during the reflow process using high reflow parameters for high yields with high I/O density fine pitch flip chips. For that reason, voids were observed on TV-2 without eutectic solder and no-flow underfill in void formation study. DSC measured heat flow diagrams of sample A (without solders...